1. Field of the Invention
The present invention relates to a stacked capacitor, and a method of forming the stacked capacitor as well as a semiconductor device using the stacked capacitor and a circuit board using the stacked capacitor.
2. Description of the Related Art
For allowing the large scale integrated circuit to exhibit a high frequency and high speed performance, it is essential that the clock signal has a high frequency. Such high frequency clock signal, however, causes a voltage drop due to a resistance R and an inductance L of an interconnection between a power supply and the large scale integrated circuit. The voltage drop is represented by the following equation (1).
xcex94V=Rxc3x97xcex94i+Lxc3x97di/dtxe2x80x83xe2x80x83(1) 
where xcex94V is the voltage drop, R is the resistance of the interconnection between the power supply and the large scale integrated circuit, L is the inductance of the interconnection between the power supply and the large scale integrated circuit, di/dt is the rate of variation of the load or the quantity of the variation of the load per a unit time.
The above equation means that if R, L and di/dt are large, then the voltage drop xcex94 V is large. The clock frequency for the advanced large scale integrated circuit is likely to be extremely high, for example, at least a few hundreds MHz. A rising time xe2x80x9ctrxe2x80x9d of a pulse waveform in digital circuit is substantially equivalent to a load variation time xe2x80x9cdtxe2x80x9d. If the clock frequency is high, the rising time xe2x80x9ctrxe2x80x9d is short, whereby the voltage drop xcex94 V is large.
It is effective for reducing the voltage drop that a capacitor is connected in parallel to the large scale integrated circuit. This capacitor is generally so called to as decoupling capacitor. If the clock frequency of the large scale integrated circuit is high, this makes it difficult that the power supply temporary compensates the dropped voltage due to the load variation. For this reason, if the clock frequency of the large scale integrated circuit is high, the decoupling capacitor is provided for compensating the dropped voltage due to the load variation.
Assuming that the decoupling capacitor is free of a self-inductance and an internal resistance, it is possible that a charge Q(=Cxc3x97V) charged in the decoupling capacitor is supplied to the large scale integrated circuit at the same time when the load variation appears, whereby the voltage variation of the large scale integrated circuit becomes substantially zero.
Actually, however, the self-inductance of the decoupling capacitor is not zero. This means that an LC resonance is caused at an LC-resonant frequency. In the higher frequency range than the LC-resonant frequency, the decoupling capacitor does not work. For this reason, if the clock frequency of the large scale integrated circuit is risen, it is necessary that the LC-resonant frequency xe2x80x9cfxe2x80x9d of the decoupling capacitor is also risen. The LC-resonant frequency xe2x80x9cfxe2x80x9d of the decoupling capacitor is represented by the following equation (2).
f2=1/(4xc3x97xcfx802xc3x97Lxc3x97C)xe2x80x83xe2x80x83(2) 
It is, therefore, preferable that the capacity C and the inductance L of the decoupling capacitor are small. A stacked ceramic capacitor has often been used as the decoupling capacitor because the stacked ceramic capacitor has a small impedance at a high frequency range and a small capacitance of at most 0.1 micro-F. The stacked ceramic capacitor is smaller in not only equivalent series resistance but also self-inductance than an electrolytic capacitor. For example, the decoupling capacitor for compensating the voltage drop of the large scale integrated circuit may be the stacked ceramic capacitor which has a capacitance C=0.01 micro-F and a self-inductance L=0.4 nH. This capacitor has an LC-resonant frequency xe2x80x9cfxe2x80x9d=about 80 MHz, which is calculated from the equation: (2xcfx80f)2xc3x97Lxc3x97C=1.
A conventional technique for reducing the self-inductance L of the capacitor is disclosed in Nikkei Electronics, April, 1999, vol. 19, pp. 144-156. As the thickness of the dielectric layer is thin, then the self-inductance is small. In this view points, thin film capacitors have been used for the semiconductor devices. Japanese laid-open patent publications Nos. 11-45822 and 8-97360.
Japanese laid-open patent publications Nos. 7-326536 and 8-17675 disclose that in order to reduce the self-inductance of a chip type stacked ceramic capacitor, an internal electrode is shaped in such a rectangle that a ratio of a short side xe2x80x9cAxe2x80x9d to a long side xe2x80x9cBxe2x80x9d is at most 0.5, and vias are formed over and under the internal electrode, and further substrate electrodes are aligned in a center region of a bottom surface of the chip type stacked ceramic capacitor.
Japanese laid-open patent publications Nos. 7-37757 and 6-314634 disclose a capacitor array for a high density package, wherein a floating capacitance between adjacent two of capacitor units is reduced. Japanese laid-open patent publication No. 6-283384 discloses another capacitor array adjusted for a narrow pitch of the integrated circuit. Japanese laid-open patent publication No. 11-97291 discloses another capacitor array with a reduced electromagnetic interference between adjacent two of the electric function devices.
In recent years, a large current supply to the large scale integrated circuit for exhibiting the high speed performance is needed. Two different large scale integrated circuits are now considered. It is assumed that a first large scale integrated circuit (A) has a switching frequency of 100 MHz, a maximum consumption power of 4V and a power voltage of 3.3V. It is also assumed that a second large scale integrated circuit (B) has a switching frequency of 500 MHz, a maximum consumption power of 18V and a power voltage of 1.8V. The necessary capacitance of the decoupling capacitor for compensation of the voltage drop appearing during a single clock will be calculated. A current rising time xe2x80x9ctrxe2x80x9d is approximately represented by the following equation (3).
tr=xc2xcfxe2x80x83xe2x80x83(3) 
where xe2x80x9cfxe2x80x9d is the clock frequency.
The necessary capacitances xe2x80x9cCxe2x80x9d for compensations to the voltage drop of the power voltage to be supplied to the first and second large scale integrated circuits (A) and (B) may be calculated as follows by using the equation: xcex94Q=Cxc3x97xcex94V=Ixc3x97tr. In case of the first large scale integrated circuit (A), the necessary capacitances xe2x80x9cCxe2x80x9d is 4Axc3x97(0.35/(1xc3x97108s))/s))/(3.3Vxc3x975%)=0.085 micro-F. In case of the second large scale integrated circuit (B), the necessary capacitances xe2x80x9cCxe2x80x9d is 18Axc3x97(0.35/(0.5xc3x97109s))/(1.8Vxc3x975%)=0.14 micro-F. As the clock frequency for the large scale integrated circuit is high and the consumption power is also large, then the necessary capacitance of the decoupling capacitor is large. If, however, only the capacitance of the decoupling capacitor is increased without increasing the self-inductance, then the LC-resonant frequency xe2x80x9cfxe2x80x9d is decreased.
Therefore, if the decoupling capacitor for compensation to the load variation of the large scale integrated circuit has a small self-inductance, then this means it easy to obtain a high LC-resonant frequency xe2x80x9cfxe2x80x9d.
In Japanese laid-open patent publications Nos. 11-45822 and 8-97360, it is disclosed that a thin film capacitor has a thin film dielectric film which has a high dielectric constant to obtain a low self-inductance and a large capacity as well as a higher LC-resonant frequency than the normal stacked ceramic capacitor. This thin film capacitor is, however, disadvantageous because of the difficulty of packaging the capacitor onto the board. Also, the process for forming the thin film capacitor is costly process. It is desirable to realize a non-expensive method for forming the thin film capacitor.
In Japanese laid-open patent publications Nos. 7-326536 and 8-17675, the chip-type stacked ceramic capacitor has a low self-inductance. The cost of the process for forming the capacitor is relatively low. The chip-type stacked ceramic capacitor is unsuitable for high density packaging for the narrow pitch of the large scale integrated circuit because of a single alignment of terminal electrodes for electrical connection to a substrate with a limited chip packaging area of 3.2 mmxc3x971.6 mm.
The interconnection between the decoupling capacitor and the large scale integrated circuit has an inductance. In order to reduce the inductance, it is effective to shorten the interconnection between the decoupling capacitor and the large scale integrated circuit. The terminal electrodes for electrical connection to the substrate are provided along a single edge of the bottom surface of the chip-type stacked ceramic capacitor. This structure makes it difficult to further make the distance between the decoupling capacitor and the circuit board shorter than the thickness of the board.
In the above circumstances, the development of a novel stacked capacitor free from the above problems is desirable.
Accordingly, it is an object of the present invention to provide a novel stacked capacitor free from the above problems.
It is a further object of the present invention to provide a novel stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is a still further object of the present invention to provide a novel stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is yet a further object of the present invention to provide a novel stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is further more object of the present invention to provide a novel stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is more over object of the present invention to provide a novel stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor reduces a signal transmission delay.
It is still more of the present invention to provide a novel method of forming a stacked capacitor free from the above problems.
It is yet more object of the present invention to provide a novel method of forming a stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is another object of the present invention to provide a novel method of forming a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is yet another object of the present invention to provide a novel method of forming a stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is further another object of the present invention to provide a novel method of forming a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is furthermore another object of the present invention to provide a novel method of forming a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor reduces a signal transmission delay.
It is an additional object of the present invention to provide a novel semiconductor device including a stacked capacitor free from the above problems.
It is an additional object of the present invention to provide a novel semiconductor device including a stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is an additional object of the present invention to provide a novel semiconductor device including a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is an additional object of the present invention to provide a novel semiconductor device including a stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is an additional object of the present invention to provide a novel semiconductor device including a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is an additional object of the present invention to provide a novel semiconductor device including a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor reduces a signal transmission delay.
It is an additional object of the present invention to provide a novel circuit board including a stacked capacitor free from the above problems.
It is an additional object of the present invention to provide a novel circuit board including a stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is an additional object of the present invention to provide a novel circuit board including a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor has a high capacity for a unit packaging area.
It is an additional object of the present invention to provide a novel circuit board including a stacked capacitor being placed in a peripheral region of a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is an additional object of the present invention to provide a novel circuit board including a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor serves as a decoupling capacitor for compensating a voltage drop upon variation in load of the large scale integrated circuit, and the stacked capacitor allows a reduction of a total inductance of the capacitor and a wiring.
It is an additional object of the present invention to provide a novel circuit board including a stacked capacitor being placed as an interposer between a circuit board and a large scale integrated circuit exhibiting a high speed performance, wherein the stacked capacitor reduces a signal transmission delay.
A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal electrodes stacked in multi-levels in the dielectric layer, and the first internal electrodes being electrically connected to a power line; second internal electrodes stacked in multi-levels in the dielectric layer, and the second internal electrodes being electrically connected to a ground line; vias in the dielectric layer, so that the terminal electrodes being electrically connected through the vias to the first and second internal electrodes.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.